Principal Investigator Tomas Palacios
Stemming from their high breakdown voltages, large power densities, and high efficiency, GaN devices have quickly grown in popularity over the last two decades. With uses in millimeter wave applications like radar, satellite communication, and electronic warfare, the ever-increasing demand for high power devices that oper- ate over large bandwidths requires that new transistor technology is created. Since vertical device dimensions and doping can be carefully controlled during wafer growth, a vertical design is ideal for RF devices which need short gate lengths. Moreover, by utilizing the vertical dimension, we can achieve excellent power density at millimeter-wave frequencies with minimal die area, and since most transport occurs through the bulk of the material, we also expect thermal management and reliability improvements when compared to the traditional GaN high electron mobility transistor (HEMTs). In this project, we adopt the design of recently developed vertical GaN transistors, which were initially optimized for high power applications, and modify them for improved RF performance.
Another important benefit of a vertical fin design is the ability for threshold voltage engineering. In RF devices, an important metric to non-linearity is gm" (the second derivative of device transconductance), which is ideally flat. One method for correcting this is through threshold voltage engineering where devices of varying VT are connected in parallel. Since shifting VT also shifts the peaks of gm", with careful design, the peaks of one transistor’s gm’’ can effectively cancel those of another when superimposed. The resultant device will then have a flatter transconductance response with improved RF performance. Through the fin-based design of the transistors in this project, the transconductance can be adjusted by simply altering the width of each fin, thus allowing for optimized large signal response for RF applications.
At MTL, we are fabricating the first vertical GaN fin RF transistors. For this, we are using electron beam lithography paired with a combination of dry and wet etching to achieve 100-300 nm tall fins with very smooth and vertical sidewalls. A molybdenum gate allows for a well-controlled etch-back process which coats only the sidewalls in metal. Further dry/wet etching can then be used to access the highly doped drain layer, which was defined during wafer growth. With the gate, source, and drain all on the top surface, this design will be compatible with GaN on Si technology, capable of significantly reducing material costs.