Principal Investigator Stephen Ward
The Raw Router is a high-performance router built using the Raw microprocessor. The goal of the raw router is to explore the capabilities and performance of different router designs using a general-prupose parallel architecture. Initial results show that our unoptimized router has a throughput of 3.2Gb/s.
For the past several years, Internet Service Providers have generally reported that their number of customers doubled annually and that the bandwidth used per customer was also increasing. In recent months, this trend has further accelerated, as more and more users switch to broadband Internet connections. Research in transmission link technologies has led to continuous improvements of link bandwidths, which has allowed for link capacities to meet these demands. However, the speeds of the routers connecting these fast links has not been keeping pace with the increase in bandwidth. For highspeed networks, the routers are becoming the bottleneck, as routers are pushed to meet the demand of ever faster links.
Traditional router designs fail to match faster link demands because the component speeds in superscalar routers do not scale: they increase at the rate of Moore’s Law. Processor speeds are not increasing fast enough to allow the router to perform per-packet processing. To meet the demands for faster routers, vendors use specialized hardware to deal with this problem. Current routers use dedicated packet processing hardware to process the packets as they flow through the data plane. The Raw Router, however, uses the explicit parallelism of the Raw architecture to overcome these scaling problems.
The router architecture exploits the raw’s rich programmable interconnects, internal speed-up and explicit parallelism in the raw chip to achieve high-performance without specialized hardware support for router-specific functions.
This example layout has four static pipelines, each entailing four stages corresponding to a row of tiles. This layout uses a combination of dynamic routing, pipelining and static DMA channels to achieve high performance.
Several key parts of the Raw Router have been completed. An initial implementation of the data plane forwarding path has been completed. We are currently working on an optimized version of the router taking advantage of Raw’s ability to stream data to and from memory using a DDR streaming protocol.
We will compare the Raw Router to several other architectures. These include a router built using the Intel IXP1200 network processor. The IXP1200 has six dedicated packet processing microengines, as well as a StrongARM processor for more complicated processing tasks. We are interested to see how our Raw router, which uses a more general microprocessor architecture, will fare against Intel’s specialized hardware. We will also compare the Raw Router to a PC router using a standard superscalar processor, with all of the packet processing done in software.