Nonlinear Modeling and Compenstaiton Architectures for Analog Front-Ends: Circuit and System Techniques for On-Chip Interconnects

In this project we are developing design and modeling methodologies for identification and compensation of analog front-end nonlinearities in deep sub-micron processes. Examples include nonlinear modeling and VLSI compensation architectures for mm-wave Power Amplifiers, impedance modulating energy-efficient high-speed link transmit equalizers/drivers, and other analog components. Of particular interest are compensation architectures that operate at high-throughputs (e.g. mm-wave baseband units and high-speed link circuits), where traditional digital signal processing techniques perform poorly.

In recent high performance processor design, cross-hierarchical optimization of on-chip networks and overall chip architecture improves the performance-power efficiency significantly. Though equalized on-chip interconnects have been proposed to improve the network efficiency, the cross-hierarchical optimization of equalized interconnects have been a difficult problem due to design complexity.

The first effort of this project focused on a modeling and tool framework for fast design space exploration of equalized on-chip interconnects by exporting abstracted low level design parameters to a link model. Using this tool, we can explore how the transistor and wire parameters affect link performance, equalization coefficients and architecture-friendly metrics like delay, power, and throughput density. With this approach, we are able to find the best link design for target throughput, power and area constraints, thus enabling the architectural optimization of energy-efficient on-chip networks. We show optimization results comparing interconnect metrics between the LCM and the repeated interconnects using our tool. Our simulation shows that the equalized LCM interconnect is much more power efficient than the repeated interconnect for given target throughput density.

In second phase, we demonstrated two circuit techniques which enhance the power efficiency of eqaulized interconnect: charge-injecting (CI) non-linar transmitter and trans-impedance amplifier (TIA) receiver. Two test chips are taped out in 90nm CMOS technology and shows the measured eye result from the first chip.